1. Field of the Invention
The present invention relates to a semiconductor device having a circuit formed of thin film transistors (hereinafter referred to as TFTs) over a substrate having an insulating surface, and to a method of manufacturing such a semiconductor device. In particular, the present invention is preferably utilized in an electro-optical device represented by a liquid crystal display device in which a pixel portion (or a pixel matrix circuit) and a driver circuit provided over the periphery of the pixel portion are provided over the same substrate, and in an electronic apparatus having such an electro-optical device mounted thereon. It is to be noted that a semiconductor device as used herein refers to any apparatus which functions by utilizing semiconductor characteristics, and includes the above-mentioned electro-optical device and electronic apparatus having such an electro-optical device mounted thereon.
2. Description of the Related Art
Semiconductor devices having a circuit formed of TFTs over a substrate having an insulating surface have been actively developed. An active matrix liquid crystal display device is well known as a representative example of such devices. Among such devices, since a TFT with a crystalline silicon film forming an active layer (hereinafter referred to as a crystalline silicon TFT) has a high field effect mobility and can form various function circuits, electro-optical devices with such crystalline silicon TFTs integrally formed over the same substrate have been developed.
For example, in an active matrix liquid crystal display device with an integral driver circuit is provided with a pixel portion for image display, a driver circuit for image display, and the like. The driver circuit is formed of a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like formed based on a CMOS circuit. These circuits are all provided over the same substrate.
The operating conditions of the individual circuits are not necessarily the same, which follows that the characteristics required for the TFTs greatly vary. For example, the pixel portion is provided with pixel TFTs formed of n-channel type TFTs and a storage capacitance, and is driven by applying voltage to liquid crystal with the pixel TFTs being as switching elements. Since the liquid crystal is driven by alternating current, a method called as the frame inversion driving method is often adopted. In this method, the characteristic required for a pixel TFT is, in order to suppress the consumed power, to make the OFF current value (drain current passing when the TFT is OFF)sufficiently low. On the other hand, with regard to the buffer circuit of the driver circuit, since high driving voltage is applied to it, it is necessary to make its withstand voltage high in order to avoid its breakage even if high voltage is applied thereto. Further, in order to enhance the current driving capacity, it is necessary to sufficiently secure the ON current value (the drain current passing when the TFT is ON).
However, there is a problem in that the OFF current value of a crystalline silicon TFT is liable to be high. In addition, similarly to the case of a MOS transistor used in an IC or the like, deterioration such as decreasing in the ON current value and the like is observed in a crystalline silicon TFT. The main reason is hot carrier injection. Hot carrier generated due to the high electric field in the vicinity of the drain is thought to cause the deterioration.
As a TFT structure for decreasing the OFF current value, a lightly doped drain (LDD) structure is known. This is to provide a region where an impurity element is lightly doped, which is referred to as an LDD region, between a channel forming region and a source or drain region which is formed by heavily doping an impurity element.
As a means for preventing the deterioration due to the hot carrier, a so-called GOLD (gate-drain overlapped LDD) structure is known, where an LDD region is disposed so as to overlap a gate electrode through a gate insulating film. This structure alleviates the high electric field in the vicinity of the drain to prevent hot carrier injection, and thus, is effective in preventing the deterioration. For example, Mutuko Hatano, Hajime Akimoto, and Takeshi Sakai disclose on pp.523-526 in xe2x80x9cIEDM97 TECHNICAL DIGEST 1997xe2x80x9d a GOLD structure formed of side walls of silicon, and confirms that the reliability of the TFT is far superior to that of TFTs otherwise structured.
However, the required characteristics are not necessarily the same between a pixel TFT of the pixel portion and a TFT of the driver circuit such as the shift register circuit or the buffer circuit. For example, in a pixel TFT, a large reverse bias voltage (negative voltage in case of an n-channel type TFT) is applied to the gate electrode. On the other hand, a TFT of the driver circuit basically does not operate in a reversely biased condition. Further, the operating speed of a pixel TFT may be {fraction (1/100)} or less of that of a TFT of the driver circuit.
In addition, the GOLD structure has a problem in that, though it is highly effective in preventing the deterioration of the ON current value, the OFF current value is larger than that of an ordinary LDD structure. This follows that it is not preferable to apply the GOLD structure to a pixel TFT. On the other hand, an ordinary LDD structure is, though highly effective in suppressing the OFF current value, not effective in alleviating the electric field in the vicinity of the drain to prevent deterioration due to the hot carrier injection. As described above, in a semiconductor device having a plurality of integrated circuits with differing operating conditions such as an active matrix liquid crystal display device, it is not preferable to form all the TFTs as the same structure. This problem manifests itself clearly as the characteristics of crystalline silicon TFTs are improved and as higher performance of active matrix liquid crystal display devices is required.
Accordingly, the present invention is made to solve the above problem, and an object of the invention is to improve the operating characteristics and the reliability of a semiconductor device and to lower the consumed power by appropriately selecting the structure of TFTs disposed in the respective circuits of the semiconductor device depending on the function of the circuits.
As described above, according to the structure of the present invention, there is provided a semiconductor device comprising a pixel portion and a driver circuit of the pixel portion formed over the same substrate, characterized in that:
an LDD region of an n-channel type TFT of the pixel portion is disposed so as not to overlap a gate electrode of the n-channel type TFT of the pixel portion; an LDD region of a first n-channel type TFT of the driver circuit is disposed so as to overlap a gate electrode of the first n-channel type TFT;
an LDD region of a second n-channel type TFT of the driver circuit is disposed so as to at least partly overlap a gate electrode of the second n-channel type TFT; and
an offset region is formed between a channel forming region of the n-channel type TFT of the pixel portion and the LDD region of the n-channel type TFT of the pixel portion.
Also, according to another structure of the present invention, there is provided a semiconductor device comprising a pixel portion and a driver circuit of the pixel portion formed over the same substrate, characterized in that:
the driver circuit comprises a first n-channel type TFT provided such that the whole LDD region overlaps a gate electrode and a second n-channel type TFT provided such that part of an LDD region overlaps a gate electrode;
an LDD region of an n-channel type TFT forming the pixel portion is provided such that the whole of the LDD region does not overlap a gate electrode at all; and
an offset region is formed between a channel forming region of the n-channel type TFT of the pixel portion and the LDD region of the n-channel type TFT of the pixel portion.
According to the structure of the present invention, it is characterized in that an impurity element imparting n-type is contained in the LDD regions of the first n-channel type TFT and of the second n-channel type TFT of the driver circuit at a concentration larger than that contained in the LDD region of the n-channel type TFT of the pixel portion, the concentration ratio is preferable set to two to ten times as large as that contained in the LDD region of the n-channel type TFT of the pixel portion. Specifically, it is preferable that an impurity element imparting n-type is contained in the LDD regions of the first n-channel type TFT and of the second n-channel type TFT of the driver circuit at the concentration ranging of from 2xc3x971016 to 5xc3x971019 atoms/cm3 and an impurity element imparting n-type is contained in the LDD region of the n-channel type TFT of the pixel portion at the concentration ranging of from 1xc3x971016 to 5xc3x971018 atoms/cm3.
According to the structure of the present invention, it is characterized in that the offset region is formed of a semiconductor film having the same composition as that of the channel forming region abutting against the offset region, an impurity element imparting p-type may be contained in the offset region at the concentration ranging of from 1xc3x971015 to 1xc3x971018 atoms/cm3.
According to the structure of the present invention, a storage capacitance may be formed from a semiconductor layer connected with the n-channel type TFT of the pixel portion and containing an impurity element imparting n-type, capacitance wirings, and an insulating film between the semiconductor layer and the capacitance wirings in the pixel portion.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising a pixel portion and a driver circuit of the pixel portion formed over the same substrate, the method being characterized by comprising:
a first step of selectively doping an impurity element imparting n-type at the concentration ranging of from 2xc3x971016 to 5xc3x971019 atoms/cm3 in active layers of first and second n-channel type TFTs forming the driver circuit;
a second step of selectively doping an impurity element imparting p-type at the concentration ranging of from 3xc3x971020 to 3xc3x971021 atoms/cm3 in an active layer of a p-channel type TFT forming the driver circuit;
a third step of selectively doping an impurity element imparting n-type at the concentration ranging of from 1xc3x971020 to 1xc3x971021 atoms/cm3 in the active layers of the first and second n-channel type TFTs forming the driver circuit and in an active layer of an n-channel type TFT of the pixel portion; and
a fourth step of selectively doping an impurity element imparting n-type at the concentration ranging of from 1xc3x971016 to 5xc3x971018 atoms/cm3 in the active layer of the n-channel type TFT of the pixel portion through an insulating film covering at least the side surfaces of a gate electrode of the n-channel type TFT.
Also, according to the present invention, there is provided a method of manufacturing a semiconductor device comprising a pixel portion and a driver circuit of the pixel portion formed over the same substrate, the method being characterized by comprising:
a first step of selectively doping an impurity element imparting n-type at the concentration ranging of from 2xc3x971016 to 5xc3x971019 atoms/cm3 in active layers of first and second n-channel type TFTs forming the driver circuit and in a semiconductor layer forming a storage capacitance of the pixel portion;
a second step of selectively doping an impurity element imparting n-type at the concentration ranging of from 1xc3x971016 to 5xc3x971018 atoms/cm3 in an active layer of an n-channel type TFT of the pixel portion through an insulating film covering at least the side surfaces of a gate electrode of the n-channel type TFT;
a third step of selectively doping an impurity element imparting p-type at the concentration ranging of from 3xc3x971020 to 3xc3x971021 atoms/cm3 in an active layer of a p-channel type TFT forming the driver circuit; and
a fourth step of selectively doping an impurity element imparting n-type at the concentration ranging of from 1xc3x971020 to 1xc3x971021 atoms/cm3 in the active layers of the first and second n-channel type TFTs forming the driver circuit and in the active layer of the n-channel type TFT of the pixel portion, in the first step, an impurity element can be simultaneously doped at the same concentration as that of the semiconductor layers forming the storage capacitance of the pixel portion. Further, it is characterized in that by the second step, an n-type impurity region and an offset region sandwiched between the n-type impurity region and a channel forming region are formed in the n-channel type TFT of the pixel portion.
According to the present invention, there is provided a method of manufacturing a semiconductor device, it is characterized in that the offset region is formed in a self-aligning manner with the insulating film covering the gate electrode of the n-channel type TFT being as the mask, the thickness of the insulating film is preferably 20 to 100 nm.
FIGS. 11A to 11C are views for explaining the structure of the present invention, and explains the positional relationship between a gate electrode and an LDD region in a TFT comprising a channel forming region and the LDD region of an active layer, a gate insulating film on the active layer, and the gate electrode on the gate insulating film.
In FIG. 11A, a structure is shown provided with an active layer having a channel forming region 501, an LDD region 502, and a drain region 503, and a gate insulating film 504 and a gate electrode 505 on the active layer. The LDD region 502 is provided so as to overlap the gate electrode 505 through the gate insulating film 504. Such an LDD region is herein referred to as Lov. Lov has the action to alleviate the high electric field generated in the vicinity of the drain, can prevent the deterioration due to the hot carrier, and thus, is suitable for use in an n-channel type TFT of the shift register circuit, the level shifter circuit, the buffer circuit, and the like of the driver circuit.
In FIG. 11B, a structure is shown provided with an active layer having the channel forming region 501, LDD regions 506 and 507, and a drain region 508, and the gate insulating film 504 and the gate electrode 505 on the active layer. The LDD region 506 is provided so as to overlap the gate electrode 505 through the gate insulating film 504. The LDD region 507 is provided so as not to overlap the gate electrode 505. Such an LDD region is herein referred to as Loff. Loff has the action to decrease the OFF current value. The structure provided with Lov and Loff can prevent the deterioration due to the hot carrier and, at the same time, can decrease the OFF current value. This is suitable for use in an n-channel type TFT of the sampling circuit of the driver circuit.
In FIG. 11C, a structure is shown where an active layer is provided with the channel forming region 501, an offset region 509, an LDD region 510, and a drain region 511. The LDD region 510 is provided so as not to overlap the gate electrode 505 and is off the gate electrode 505 by the width of the offset region 509. The composition of the offset region 509 is the same as that of the channel forming region 501. By forming the offset region and providing Loff in this way, the OFF current value can be effectively decreased, and thus, this is suitable for use in an n-channel type TFT of the pixel portion. The concentration of the impurity element imparting n-type in the LDD region 510 of the pixel portion is preferably xc2xd to {fraction (1/10)} of that in the LD regions 502, 506, and 507 of the driver circuit.